1. Field of the Invention
The present invention relates to a semiconductor device structure and semiconductor device fabrication process.
2. Description of the Related Art
Integrated circuits are generally fabricated by forming circuit elements in a semiconductor substrate, then forming one or more metal interconnection layers above the substrate. Often the circuit elements are field-effect transistors having gate electrodes insulated from the substrate by a thin oxide film referred to as a gate oxide. The metal interconnection layers are insulated from one another, and from the semiconductor substrate, by insulating films referred to as interlayer dielectric films, or simply as interlayer dielectrics. The uppermost metal interconnection layer is covered by a surface passivation film.
The interlayer dielectrics and surface passivation film are often formed by chemical vapor deposition (CVD), a technique in which the substrate is heated, and source gases react near the surface the substrate to form a desired material that is deposited on the substrate. Various types of CVD are known, including low-pressure CVD (LP CVD), atmospheric-pressure CVD (AP CVD), plasma-enhanced CVD (PE CVD) and high-density plasma CVD (HDP CVD). The plasma types of CVD (PE CVD and HDP CVD) have the advantage of being performable at a lower temperature than the other types of CVD (LP CVD and AP CVD). Since the mid-1990s, HDP CVD, which can effectively fill the narrow spaces between adjacent gate electrodes and adjacent interconnecting lines without creating bread-loaf shapes or cusps, has come into widespread use in fabrication processes with half-micrometer and smaller design rules. The reason for the effectiveness of HDP CVD is that the substrate is not only heated but also electrically charged, drawing the plasma down to etch unwanted parts of the deposited film.
This feature of HDP CVD leads to a problem however. During the HDP CVD process, the charge of the plasma is conducted through the metal interconnecting lines and gate electrodes to the gate oxide. In recent devices, the gate oxide is extremely thin, and is vulnerable to damage from the plasma charge. Although the damage mechanism is not completely understood, the damage is thought to result from the trapping of charge in the gate oxide film. Electron microscope studies by the inventor have confirmed that gate oxide damage occurs as a result of HDP CVD.
Such damage can lead to failure of devices in factory tests, thus reducing the yield of the fabrication process, or failure in the field, reducing the reliability of the fabricated devices. Accordingly, there is a need for a fabrication process that retains the advantages of HDP CVD while avoiding damage to thin gate oxide films.
An object of the present invention is to avoid damage to gate oxide films during HDP CVD.
In the invented method of fabricating a semiconductor device, a patterned conductive layer is formed on a substrate. An initial dielectric film is then deposited by a non-etching deposition process, covering the exposed surfaces of the patterned conductive layer and the substrate. Next, a second dielectric film is deposited on the initial dielectric film by HDP CVD.
The initial dielectric film is preferably less than one hundred nanometers thick. A thin initial dielectric film can be formed without creating cusps or bread-loaf shapes, even though a non-etching deposition process is used, and without damaging the patterned conductive layer, even if a comparatively high-temperature deposition process is used.
Since the initial dielectric film covers the exposed surfaces of the patterned conductive layer, when HDP CVD is used to deposit the second dielectric film, the plasma charge is not conducted to the patterned conductive layer, and accordingly is not conducted to any gate oxide films present in the semiconductor device. Gate oxide damage is thereby avoided during HDP CVD.
The invention also provides a semiconductor device fabricated by the process described above.